1. Technical Field
Various embodiments generally relate to a semiconductor integrated circuit apparatus, and more particularly, to a semiconductor memory apparatus, and impedance calibration circuit and method thereof.
2. Related Art
Semiconductor memory apparatuses may include a receiving circuit configured to receive signals transmitted from external apparatuses. The semiconductor memory apparatuses may also include transmitting circuits configured to transmit signals from within the the semiconductor memory apparatuses to external apparatuses.
Swing widths of the signals received in the receiving circuit and transmitted from the transmitting circuit of the semiconductor memory apparatuses depend on processing rates of the semiconductor memory apparatuses. That is, as the processing rates of the semiconductor memory apparatuses are increased, the delay time required for signal transmission may be controlled and minimized through reduction in the swing widths.
However, when the swing widths of the signals are reduced, the effect on external noise may be increased, and impedance mismatching in interface stages of the semiconductor memory apparatuses may occur.
The impedance mismatching is caused from external noise, variation in the power voltage, change in the operation temperature, variation in the fabrication process, or the like.
The impedance mismatching may disturb high-speed data transmission, and as a result of the mismatching the output data of the semiconductor memory apparatuses may be distorted.